Hello, I'm Ching Lun Chou

Master degree from NCKU
I major in

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Hello, My name is

Chou, Ching-Lun (周敬倫)

I come from Kaohsiung city. I got my master degree in electrical engineering from National Cheng Kung University in last July. During my time there, I majored in writing Verilog code, video/image processing. My research task focused on the 3D video/image processing by utilizing FPGA boards. Since the difference between hardware and software design, we must reach an agreement on the specification at first. Through the teamwork, I eventually made the higher precision of stereo matching combined the brand-new format. The processing speed could achieve 60 frames per second with the resolution of 1920 × 1080 and 64 disparity levels in 160 MHz. Moreover, I have four years of experiences in digital IC contest and qualified the final in 2015. Therefore, I’m a true team player.

In regard to my personality, I always dedicate my passion to what I like. For example, during my military service, I spent my spare time creating a personal blog by using web code I never learned before. Up to now, I’ve posted six articles and the total page views are more than ten thousand in two months. That’s why my friends always say that I am a true go-getter.


Education
National Cheng Kung University

Bachelor of Electrical Engineer

Sept. 2010 - Jun. 2014

National Cheng Kung University

Master of Electrical Engineer(VLSI/CAD)

Sept. 2014 - Aug. 2016


Experience
Teaching Assistant

Foreign Languages and Literature, NCKU

Oct. 2014 - Sept. 2015

Teaching Assistant

Electrical Engineering, NCKU

Feb. 2016 - Jul. 2016

Mr.Joker Blogger

My Personal Blog

Mar. 2017 - NOW


My Skills
Video processing
Intermediate
Verilog
Skillful
FPGA
Good
System design
Average

Researches

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Stereo Matching with Double Refinements for Centralized Texture Depth Packing and Their VLSI Implementations

In this thesis, a stereo matching with double refinements which combines centralized texture depth packing (CTDP) system is proposed. In the traditional stereo matching algorithm, left-right check in the refinement process is unable to detect mismatching errors usefully. In order to raise the accuracy, texture-based detection is proposed in this thesis to flag mismatching errors for achieving high accuracy. In addition, the CTDP format which has no corresponding hardware implementation is proposed, recently. This thesis proposed the CTDP system combined with a stereo matching with double refinements.

projects

Depth Image Based Rendering

Research and compare between the tradition 3D rendering and DIBR.

Super Resolution

Research and compare among many interpolations.

Pipeline CPU

Design and synthesis the basic model of pipeline CPU.

Activities

2017 TOEIC Score Report


2016 Excellent Teaching Assistant Award


2016 TJCAS Best Poster Design


2015 Logic Synthesis with Design Compiler Certification


2015 Integrated Circuit Design Contest


2014 Teaching Assistant Certification


2012 2nd Kaohsiung NCKU Camp Certificate